Numerical types
Integer and fixed-point types specify widths and signedness. Fixed-point conversion specifies rounding and overflow behavior.
ZLANG HDL / LANGUAGE
Language and compiler
Numerical types, clocked state, protocols, implementation constraints, and SystemVerilog generation.
Clocked state
Registers declare clock/reset ownership. Next-state assignments and atomic rules define state updates.
Protocol connections
Typed endpoints describe module connections. Clock-domain crossings and protocol adapters have documented restrictions.
Implementation selection
The implement construct selects supported implementations under constraints such as DSP count, latency, and initiation interval.
Verification results
Formal support depends on the property and specialization. A bounded pass is not an unbounded proof.
SystemVerilog output
The compiler emits SystemVerilog for supported designs. Synthesis, timing analysis, and physical implementation use external tools.
COUNTER SOURCE AND OUTPUT
Start with
eight bits.
The count register stores eight bits. The output y reads count. Each update increments count and explicitly truncates the result to eight bits.
Try this example →ZLang source
Public source examples/counter.zhl
module Counter {
clock clk
reset rst
reg count : u8 = 0
out y : u8
y = count
count <- truncate(count + 1)
}
The original example, unchanged from the linked revision.
Compiler check
Recorded output zlang examples/counter.zhl --top Counter --check
zlang: ok: examples/counter.zhl (top Counter; syntax and semantics valid)
Recorded process exit status: 0. Syntax and semantic checking only.
Generated SystemVerilog
Recorded output zlang examples/counter.zhl --top Counter --systemverilog build/Counter.sv
`default_nettype none
module Counter (
input wire logic clk,
input wire logic rst,
output logic [7:0] y
);
// Generated from backend-independent typed ZLang IR.
logic [7:0] count;
always_ff @(posedge clk) begin
if (rst) begin
count <= 8'd0;
end else begin
count <= 8'(({{1{1'b0}}, count} + 9'd1));
end
end
assign y = count;
endmodule
`default_nettype wire
Recorded process exit status: 0. Output file: build/Counter.sv.
ZLang is an experimental alpha. Read the known limitations and Language Reference for supported combinations.
Know the current limits.
- No runtime procedural
if, implicit numeric casts, or general HLS scheduler. - No automatic clock-domain-crossing insertion. Cross-domain storage and protocol support are limited to documented profiles.
- Formal results apply to specific properties and configurations. A successful compiler check does not establish timing closure or hardware correctness.