Hardware projects
ZTPU, ZRISC-V32, and ZRISC-V64: hardware designs in ZLang HDL, with project availability and validation status.
ZTPU, ZRISC-V32, and ZRISC-V64 use ZLang HDL to describe accelerator and processor hardware. ZTPU source and a simulation demo are available. The CPU sources are private. Project status and licensing are listed below.
ZTPU
Fixed-point accelerator
A ZLang HDL accelerator with queued matrix, vector, and Adam engines, plus a cycle-level MicroGPT inference demo.
The reference arithmetic is Q16. The public demo runs the queued hardware engines in the native simulator; the host handles tokenization, tensor movement, and sampling. Numerical results differ from the original floating-point model.
PolyForm Noncommercial 1.0.0; commercial terms are separate.
Source repository ↗
ZRISC-V32
32-bit RISC-V processor
A 32-bit RISC-V CPU development project written in ZLang HDL.
The source is private. Public distribution details and supported ISA extensions are not published on this site.
Private development; contact the project for availability.
Ask about ZRISC-V32 →
ZRISC-V64
64-bit RISC-V processor
A 64-bit RISC-V CPU development project written in ZLang HDL.
The source is private. Public distribution details and supported ISA extensions are not published on this site.
Private development; contact the project for availability.
Ask about ZRISC-V64 →