From a counter to a transmitter

An eight-bit Counter

A real source example showing clock/reset declarations, storage, a combinational output, and an explicit next-state update.

module Counter {
    clock clk
    reset rst

    reg count : u8 = 0
    out y     : u8

    y = count
    count <- truncate(count + 1)
}

zlang: ok: examples/counter.zhl (top Counter; syntax and semantics valid)

`default_nettype none
module Counter (
  input wire logic clk,
  input wire logic rst,
  output logic [7:0] y
);
  // Generated from backend-independent typed ZLang IR.
  logic [7:0] count;
  always_ff @(posedge clk) begin
    if (rst) begin
      count <= 8'd0;
    end else begin
      count <= 8'(({{1{1'b0}}, count} + 9'd1));
    end
  end
  assign y = count;
endmodule
`default_nettype wire

zlang examples/counter.zhl --top Counter --check
zlang examples/counter.zhl --top Counter --systemverilog build/Counter.sv

Complex multiplication & streaming FFT

The FFT examples include complex multiplication and streaming transforms. The multiplication excerpt below limits DSP use to three, latency to one cycle, and initiation interval to one cycle.

product = implement {
    a * b
    intent {
        dsp <= 3
        latency == 1
        ii == 1
        minimize lut
    }
}

Resource constraints do not substitute for target-specific synthesis measurements. The example README lists supported widths, targets, and validation results.

An 802.11a-derived transmit path

Packet framing → scrambler → convolutional encoder → interleaver → constellation mapper → IFFT → cyclic prefix → complex samples.

This project tests the compiler and RTL backend using the profiles listed in its README. It does not establish complete 802.11 conformance or provide a production radio.