A typed hardware language that emits SystemVerilog.

module Counter {
    clock clk
    reset rst

    reg count : u8 = 0
    out y     : u8

    y = count
    count <- truncate(count + 1)
}

zlang: ok: examples/counter.zhl (top Counter; syntax and semantics valid)

`default_nettype none
module Counter (
  input wire logic clk,
  input wire logic rst,
  output logic [7:0] y
);
  // Generated from backend-independent typed ZLang IR.
  logic [7:0] count;
  always_ff @(posedge clk) begin
    if (rst) begin
      count <= 8'd0;
    end else begin
      count <= 8'(({{1{1'b0}}, count} + 9'd1));
    end
  end
  assign y = count;
endmodule
`default_nettype wire